王晓晓,教授,博士生导师,北京航空航天大学,电子信息工程学院

地址:柏彦大厦1813 (原1808)

Xiaoxiao (Michel) Wang, Professor, PhD Advisor, School of Electronic and Information Engineering,Beihang University

Office: 1813 Baiyan Bld

电话 Tel: (86)10-82338721

邮箱 Email: wangxiaoxiao@buaa.edu.cn



 
实验室现招收2013级硕士生,有意者可邮件联系wangxiaoxiao@buaa.edu.cn   (信息更新时间2017年2月20日)

研究方向 Research Interests

  • 以安全性和可靠性为导向的集成电路设计与测试; Security and Reliability Oriented IC Design and Test 

教育经历 Biography  

  • PhD, Department of ECE, University of Connecticut, Storrs, United States, 2007-2010
  • MS,  School of Electronic and Information Engineering,  Beihang University,  Beijing, China,  2005-2007
  • BS,  School of Electronic and Information Engineering,  Beihang University,  Beijing, China,  2001-2005

以往工作经历 Prior Academic and Industry Experiences

  • Senior IC Designieer Engineer, AISG Group, Freescale Semiconductor, Austin, United states, 2010-2014
  • Industry Mentor, Department of ECE,  University of Texas at Austin,  Austin, United States,  2014
  • Intern, ASIC Group,  Texas Instruments,  Dallas, United States, 2008

在读博士研究生 Phd Students 

  •  于丽婷 Liting Yu   
  •  孙畅     Chang Sun

在读硕士研究生 Master Students 

  • 郭玥妤 Yueyu Guo     
  • 吴亮     Liang Wu  
  • 野庆昊 Qinghao Ye      
  • 张东嵘 Dongrong Zhang     
  • 汝松昊 Songhao Ru
  • 韩玥莹 Yueying Han 

毕业硕士研究生 Graduated Master Students

  • 焦鹏远 Pengyuan Jiao     现就职英特尔(北京)             with Intel (Beijing)
  • 贡建松  Jiansong Gong     现就职中国航天科工(北京)  with CASIC (Beijing)

曾指导本科毕业生 Graduated Bachelor Students

  • 刘雨辰 Yuchen Liu            现就读 Taxas A&M University(美国)   with TAMU (United States)

 


主讲课程 Teaching

《集成电路测试与验证》             研究生选修课                                    秋季学期               课程大纲

《VLSI Test and Verification》    Graduate Level Selective Class        Fall Semester       Class Syllabus


 

主要在研项目 Major Projects

  • 面向全生命周期硬件安全保障的集成电路设计与筛选关键技术研究,国家自然科学基金重点项目,负责人,01/2017-2021/12;Critical Design and Screening Techniques for IC Life Cycle Hardware Security, Key Project of National Natural Science Foundation of China (NSFC Key Project), Leading PI
  • 可与MPSoC高度融合的片上自主测试-自主修复关键技术研究:针对自然、人为可靠性威胁,国家自然科学基金青年项目,负责人,01/2016-2018/12On-Chip Self-Test and Adaption Techniques Against Reliability Threats, Youth Fund of  National Natural Science Foundation of China (NSFC Youth Project), Leading PI
  • 集成电路失效时间(TTF)预测方法研究,航空科学基金,负责人,10/2015-10/2017Time to Failure (TTF) Prediction for Digital Circuits of 65nm and Below, Aeronautic Science Foundation of China, Leading PI

奖励 Awards

  • 2016全国测试学术会议最佳论文奖; Best Paper Awards,2016 China Test Conference
  • 2014 URSI青年科学家; Young Scientist Award, 2014 URSI
  • Best in Session Award, 2010 SRC TECHCON
  • Best Paper Award,2008 IEEE North Atlantic Test Workshop   

活动 Events


期刊论文 Journal Papers

1.      X. Wang, P., M. Sadi, D. Su, L. Winemberg, M. Tehranipoor, "TRO: An On-chip Ring Oscillator Based GHz Transient IR-Drop Monitor", IEEE transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 36(5):855-868 (2017).

2.      X. Wang, D. Zhang, D. Su, L. Winemberg, M. Tehranipoor, A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 24(5): 1716-1727 (2016).

3.      X. Wang, L. Winemberg, D. Su, D. Tran, S. George, N. Ahmed, S. Palosh, A. Dobin, M. Tehranipoor, Aging Adaption in Integrated Circuits Using a Novel Built-In SensorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 34(1): 109-121 (2015).

4.   X. Wang , M. Tehranipoor, S. George, D. Tran, L. Winemberg, Design and Analysis of a Delay Sensor Applicable to Process/Environmental
Variations and Aging Measurement,IEEE Transactions on Very Large Scale Integration Systems (TVLSI),20(8):1405-1418 (2012).

5.   Q.Shi, X.Wang, L.Winemberg, M.Tehranipoor, On-Chip Sensor Selection for Effective Speed-BinningAnalog Integrated Circuits and Signal Processing, (88): 369-379 (2016).

6.   M.Tehranipoor, H.Salmani, X.Zhang, X.Wang, R.Karri, J.Rajendran, and K.Rosenfeld, Trustworthy Hardware: Trojan Detection Solutions and Design-for-Trust Challenges, IEEE Computer, 44(7): pp 66-74 (2011).

7.   D.Su, X.Wang, Relationship between PCB Material and Power/ground Impedance, Journal of Beijing University of Aeronautics and Astronautics (EI Source Journal) Vol. 33, pp. 568-571, (2007).

 

会议论文 Conference Papers

1.      D. Zhang, M. He, X. Wang, M. Tehranipoor, Dynamically Obfuscated Scan for Protecting IPs Against Scan-Based Attacks Throughout Supply Chain, IEEE VLSI Test Symposium (VTS), 2017 (accepted).

2.      T. Rahman, D. Forte, X. Wang, and M. Tehranipoor, "Enhancing Noise Sensitivity of Embedded SRAMs for Robust True Random Number Generation in SoCs," IEEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 2016.

3.     L. Wu, X. Wang, Y. Cheng, X. Zhao, D. Su, A. Chen, Q. Shi, M. TehranipoorAES Design Improvement Towards Information Safety,  IEEE International Symposium on Circuits and Systems (ISCAS)  2016: 1706-1709.

4.      P. Jiao, D. Zhang, W. Han, Z. Tian, Z. Lv, Y. Cai, G. Shao, X. Wang: A Novel On-Chip Path Delay Difference Measurement System for Recycled IC Identification,China Test Conference (CTC) 2016: 1-4 (Best paper award).

5.      L. Yu, X. Wang, Y. Chen, X. Zhao, P. Jiao, A. Chen, D. Su, L. Winemberg, M. Sadi, M. Tehranipoor, An Efficient All-Digital IR-Drop Alarmer for DVFS-Based SoC,IEEE International Symposium on Circuits and Systems (ISCAS) 2016: 221-224.

6.      X. Wang, Donglin Su,On-chip EMI monitoring for integrated circuits of 55nm and below technologiesGeneral Assembly and Scientific Symposium (URSI GASS), 2014 XXXIth URSI, 2014.

7.      D. Su,K. Zhu,M. Niu,X. Wang, A quantified method for characterizing harmonic components from EMI spectrum, 2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC)2015.5.26-2015.5.29

8.      M. Sadi, M. Tehranipoor, X. Wang, L. Winemberg, Speed Binning Using Machine Learning And On-chip Slack Sensors, 25th ACM Great Lakes Symposium on VLSI (GLSVLSI), 155-160, 2015.

9.      Q. Shi, M. Tehranipoor, X. Wang, L. Winemberg, On-chip sensor selection for effective speed-binning, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014.

10.   X.Wang, L. Winemberg, etc., “Fast Aging Prediction during Production Test”, IEEE International Reliability Physics Symposium (IRPS) 2014:1-6.

11.   X. Wang, D. Tran, S. George, L. Winemberg, N. Ahmed, S. Palosh, A. Dobin, and M. Tehranipoor,  Radic: A Standard-Cell-Based Sensor for On-Chip Aging and Flip-Flop Metastability Measurements , IEEE International Test Conference (ITC) 2012: 1-9.

12.   X. Wang and M. Tehranipoor, "Low-Cost On-Chip Structures for Measuring NBTI Effects, Variations, Path Delay, and Noise," in Proc. 2010 SRC TECHCON, 2010 (Best in Session Award).

13.   X. Wang and M. Tehranipoor, "Novel Physical Unclonable Function Based on Process and Environmental Variations," in Proc. 2010 Design, Automation, and Test in Europe (DATE), Mar. 2010, pp. 1065-1070.

14.   X. Wang, M. Tehranipoor, and R. Datta, "A Novel Architecture for On-Chip Path Delay Measurement," in Proc. 2009 International Test Conference (ITC), Nov. 2009, pp. 1-10.

15.   X. Wang, M. Tehranipoor, and J. Plusquellic, Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions, in proc. IEEE Symposium on Hardware-Oriented Security and Trust (HOST) 2008: 15-19.

16.   X. Wang, M. Tehranipoor, and R. Datta, “Path-RO: A Novel On-Chip Critical Path Delay Measurement Under Process Variations,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2008, pp. 640-646.

17.   R. Rad, X. Wang, M. Tehranipoor,  Power supply signal calibration techniques for improving detection resolution to hardware Trojans, IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2008: 632-639.

18.   X. Wang, H. Salmani, M. Tehranipoor, and J. Plusquellic, “Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis,” IEEE International Symposium on Fault and Defect Tolerance in VLSI Systems (DFT), Oct. 2008, pp. 87-95.

19.      X. Wang, M. Tehranipoor, and R. Datta "Path-RO: On-Chip Critical Path Delay Measurement under Process Variations," in Proc. 2008 IEEE North Atlantic Test Workshop (NATW), May 2008, pp. 1-6 (Best Paper Award)

 

 

 

 

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